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  32207 ms pc 20061109-s00003 no.a0693-1/8 http://onsemi.com semiconductor components industries, llc, 2013 august, 2013 LV5609V overview the LV5609V is vertical clock driver for ccd. functions ? ternary output 2ch ? binary output 2ch ? sht output 1ch ? output on resistance : 30 typ specifications absolute maximum ratings at ta = 25 c, v ss = vm = 0v parameter symbol conditions ratings unit v dd max 6v vh max 20 v vl max -10 v maximum supply voltage vh-vl max 24 v allowable power dissipation pd max with specified substrate * 0.67 w operating temperature topr -20 to +80 c storage temperature tstg -40 to +125 c * : specified substrate : 114.3 76.1 1.6mm 3 , glass epoxy board allowable operating ratings at ta = 25 c, v ss = vm = 0v ratings parameter symbol conditions min typ max unit v dd 2.0 3.3 5.5 v vh 15 17 v vl -8.5 -7.5 -4 v supply voltage vh-vl 23.5 v cmos input high voltage v in h 0.8v dd v dd v cmos input low voltage v in l -0.1 0.4 v bi-cmos lsi vertical clock driver for ccd orderin g numbe r : ena0693 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV5609V no.a0693-2/8 electrical characteristics at ta = 25c, v dd = 3.3v, v ss = 0v, vh = 15v, vl = -7.5v, vm = 0v, unless otherwise specified ratings parameter symbol conditions min typ max unit i dd v dd pin 1 a ih vh pin 10 a static current drain il vl pin 1 a i dd v dd pin see *1 and *2. 1 ma ih vh pin see *1 and *2. 2.4 4.5 ma dynamic current drain il vl pin see *1 and *2. 3 5 ma rl i o = +10ma 20 30 rm i o = 10ma 30 45 rh i o = -10ma 30 40 output on resistance rsht i o = -10ma 30 40 tplm no load 200 ns tpmh no load 200 ns tplh no load 200 ns tpml no load 200 ns tphm no load 200 ns propagation delay time tphl no load 200 ns vl vm v1, v3 see *1. 800 ns ttlm vl vm v2, v4 see *1. 800 ns ttmh vm vl v1, v3 see *1. 800 ns rise time ttlh vl vh sht see *1. 200 ns vm vl v1, v3 see *1. 800 ns ttml vm vl v2, v4 see *1. 800 ns tthm vh vm v1, v3 see *1. 800 ns fall time tthl vh vl sht see *1. 200 ns *1 : refer to the ccd equivalent load shown below. *2 : refer to the timing waveform on page 7. v1 (ternary) v2 (binary) v4 (ternary) v3 (binary) sht 2000pf 2000pf 1000pf 3000pf 3000pf 1000pf 2000pf 2000pf 1600pf
LV5609V no.a0693-3/8 package dimensions unit : mm (typ) 3179c 6.5 4.4 6.4 0.22 0.65 (0.33) 110 11 20 0.5 0.15 1.5max 0.1 (1.3) sanyo : ssop20(225mil) 0 0.8 0.67 0.30 0.4 0.2 0.6 1.0 ? 20 80 60 20 40 010 0 ambient temperature, ta ? c allowable power dissipation, pd max ? w pd max ? ta specified circuit board : 114.3 76.1 1.6mm 3 glass epoxy board
LV5609V no.a0693-4/8 pin assignment pin function pin no. name mode 1 v3 level shift output (ternary vh, vm, vl) 2 v2 level shift output (binary vm, vl) 3 v1 level shift output (ternary vh, vm, vl) 4 vm gnd for output 5 nc 6 vh hi power supply (15v system) for output 7 xv1 v1 transfer pulse input 8 xsg1 v1 read pulse input 9 xv2 v2 transfer pulse input 10 xv3 v3 transfer pulse input 11 xsg3 v3 read pulse input 12 xv4 v4 transfer pulse input 13 nc1 14 xsht sht pulse input 15 v dd power supply (3.3v system) for input buffer 16 v ss gnd for input buffer 17 vl lo power supply (-7.5v system) for output 18 nc 19 sht level shift output (binary vh, vl) 20 v4 level shift output (ternary vm, vl) ssop20 LV5609V top view 1 v3 2 v2 3 v1 4 vm 5 nc 6 vh 7 xv1 8 xsg1 9 xv2 10 xv3 20 v4 19 sht 18 nc 17 vl 16 vss 15 vdd 14 xsh t 13 nc 12 xv4 11 xsg3
LV5609V no.a0693-5/8 block diagram logical function table input output xv1 xv3 xsg1 xsg3 xv2 xv4 xsht v1 v3 v2 v4 sht l l x x vh x x l h x x vm x x h l x x vl x x h h x x vl x x x x l x x vm x x x h x x vl x x x x l x x vh x x x h x x vl 9 6 5 7 4 3 2 1 20 12 13 14 15 16 17 18 21 30 30 30 30 input buffer v dd xv1 xsg1 xv2 xv3 xsg3 xv4 xsht v ss vh v1 v2 vm v3 v4 sht vl 0.1 f 1 f 1 f level shift & output buffer 30
LV5609V no.a0693-6/8 timing chart xsg1 xsg3 xv1 to xv4 v dd v ss v dd v ss 50% 50% 50% tpmh ttlm vh 90% ttml v1 v3 10% 90% tplm vm vl 10% tpml 10% 90% tplm vm vl tpml ttlm v2 v4 ttml xsht v dd v ss 50% 50% 10% 90% tplh vh vl tphl ttlh sht tthl ttmh tphm tthm
LV5609V no.a0693-7/8 63.5 s 2 s 127 s 2.5 s 16.7ms 2.5 s 63.5 s 2 s xv3 xv1 xv2 xv4 xsg1 xsg3 xsht xv1 xv2 xv3 xv4 0 s0.7 s1.4 s2.1 s2.8 s3.5 s4.2 s4.9 s ccd equivalent load measurement timing waveform enlarged view of overlapped portion
LV5609V ps no.a0693-8/8 on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.


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